Timing closure refers to the process of making changes to an initial integrated circuit design to get rid of timing violations. Typically, a static timing analysis software tool is employed to determine all the timing violations. Changes are made to improve the design and static timing analysis is iteratively invoked until all violations have been addressed. These changes are also referenced to as “moves.” Making moves to improve the timing of the circuit will be referred hereinafter as optimization.
Examples of changes made to achieve timing closure include buffer insertion, gate sizing, assignment of wires to metal layers, pin swapping and pad cell (or “delay cell”) insertion. Some moves improve the timing characteristics of the design and others make timing worse, so that the timing closure process is often “timing driven”, meaning that the static timer is queried to determine which changes improve the design and which do not. In general, the iterative implementation of changes in a timing-driven manner can be made manually by a designer, or by a software Electronic Design Automation tool.
For an integrated circuit to be free of timing violations, numerous timing tests associated with the circuit design must be met. Associated with each timing test is a timing slack, which is computed by the static timing analysis (STA) tool. Positive slack signifies that the timing is met, and negative slack implies a timing violation. The process of optimization consists of iteratively making moves until a positive slack is achieved for each timing test. STA software tool typically supports slack queries to aid in the optimization process.
Manufacturing and environmental variations significantly complicate the timing closure. Manufacturing variations will be referenced hereinafter as “process variations.” Variations are handled by an STA program by utilizing either multi-corner methods or statistical embodiments. The corner is a unique setting of process and environmental variables, and multi-corner timing implies that timing analysis is repeated at multiple corners and the worst (i.e., smallest) slack across all corners must be positive for closure. In a statistical timing, some or all variations are treated statistically, i.e., as probability distributions. The resulting statistical slack is “projected” to obtain the worst slack across the space of manufacturing and environmental variations, and the statistical slack must be positive to achieve closure.
For conventional optimization methods, timing are queried after every move, and the moves that result in an improved timing are accepted, while those that worsen the timing are rejected. One timing test is targeted at a time and various moves are tried in an iterative manner until either a positive slack is achieved or the present timing test is skipped in order to make progress on other timing tests. In this conventional method, the static timing analysis software typically updates timing information incrementally to answer timing queries made after each move. Incremental timing implies that the timing tool performs minimal computation in order to answer the timing query after a circuit change. In another conventional method, a plurality of moves is “batched up” and timing is then checked after applying all the changes to the design.
Both conventional methods suffer from significant drawbacks. In the aforementioned first method, the computer run time of updating timing and answering timing queries after each design change can be prohibitive, because millions of changes can be attempted in a single optimization run and timing queries must be answered every single time. A second drawback is that each proposed change provides a different amount of benefit at different process corners. If the multi-corner or statistical timing must be repeated to evaluate the benefit of each proposed change, the computational burden can become overwhelming. If single corner timing is used to guide the optimization, then the timing violations at other corners may not be addressed and may in fact get worse. Thus, the optimization may improve the timing at the single corner considered, but make timing worse at other corners, and may “ping pong” back and forth without making any real progress. This drawback of prior art embodiments highlights the difficulty of timing closure in the presence of variations. A third weakness of prior art methods is that there is no easy way to decide which type of move is most effective in any given situation.
Programs will typically try either buffering or sizing or layer assignment or other types of moves in different heuristically selected orders to see which yields most benefit. The selected order applies to all timing violations. Presently, violations that benefit from a different order of moves cannot be achieved with conventional methods. As a result, conventional embodiments are inefficient due to applying the same order of types of moves to all the timing violations. This inefficiency manifests itself as longer run times and sub-optimal results in terms of timing, power and area of the integrated circuit. The heuristic ordering of moves makes the optimization results inconsistent, untrustworthy and subject to chance.
Other conventional methodologies also suffer from another significant drawback. As moves are accepted and design changes are implemented, the timing information corresponding to the changed circuit is not available. Therefore, there is no clear timing guidance for the rest of the moves in the “batch” of moves. As in this conventional embodiment, there is no guarantee that various corners or portions of the space of manufacturing variations will have fixed timing violations. As previously stated, there is no intuitive approach for which type of change will be most beneficial in any given situation.
Conventional embodiments often use exhaustive methods. For example, all sizes of a buffer may be inserted one at a time with a timing query following each insertion to determine the best size. In many instances, they are limited by the use of heuristic methods to optimize moves in various different orders to fix the timing violations. For instance, conventional methods may use delay pad cell insertion first, followed by buffering, gate sizing and finally pin swapping. The heuristic order is applied to all the timing violations, which is wasteful because different timing violations benefit from different types of moves, and trying moves in the same order across all the timing violations, which is inefficient.
Thus prior art embodiments have a relatively low fraction of moves that are accepted, and they create sub-optimal designs by inserting buffers, in instances where gate sizing may be a more efficient way to fix a particular timing violation.
In view of these and other reasons, conventional embodiments have failed to achieve timing closure in the presence of manufacturing and environmental variations, and suffer from significant drawbacks.
Accordingly, methods have been proposed in the literature, but generally have not been practiced in industry. Thus, there is a need for methods capable of providing a statistical optimization of integrated circuit designs.